1. Field of the Invention
The present invention relates to power factor correction (PFC) converters, and more particularly, relates to a switching controller of PFC converters.
2. Description of Related Art
FIG. 1 schematically shows a circuit of a PFC converter. A bridge rectifier 10 rectifies a line voltage VAC into an input voltage VDC. The input voltage VDC is supplied to an inductor 20. A low-pass filter 80 receives the input voltage VDC to generate a line-effective voltage VRMS. A rectifier 30 is connected between the inductor 20 and an output of the PFC converter. A bulk capacitor 40 is coupled between the output of the PFC converter and a ground reference to provide a bulk voltage VBULK. The bulk voltage VBULK is a boosted voltage which is higher than the input voltage VDC. The bulk voltage VBULK is used to provide power to a load of the PFC converter, for example, a PWM circuit 60. A power switch 70 coupled to a joint of the inductor 20 and the rectifier 30 performs energy switching to correct the line current of the PFC converter and regulate the bulk voltage VBULK. A voltage divider 50 including resistors 51 and 52 connected in series is connected between the output of the PFC converter and the ground reference.
A switching controller 100 has a line-voltage terminal RMS, a line-current terminal IAC, a current-sense terminal IS, a compensation terminal EA, a feedback terminal FB, and an output terminal OUT. The low-pass filter 80 receives the input voltage VDC and provides the line-effective voltage VRMS to the line-voltage terminal RMS. The line-current terminal IAC is coupled to the bridge rectifier 10 via a line resistor 12 for receiving a line-reference current IAC. A sense resistor 11 is coupled to the bridge rectifier 10. The current-sense terminal IS is connected to a joint of the sense resistor 11 and the bridge rectifier 10 to obtain a sense voltage −VS. The sense voltage −VS represents an overall system current IS of the PFC converter. A compensation capacitor 45 is connected to the compensation terminal EA for frequency compensation. A voltage-loop error signal VEA is obtained across the compensation capacitor 45. The feedback terminal FB receives a feedback voltage VFB from a joint of the resistor 51 and the resistor 52. The switching controller 100 generates a switching signal VG at the output terminal OUT in response to the feedback voltage VFB, the line-effective voltage VRMS, the line-reference current IAC, and the sense voltage −VS.
FIG. 2 schematically shows a circuit of a conventional switching controller 100a. The switching controller 100a comprises a current-command circuit, a switching-control circuit, a programmable feedback circuit, a light-load detector 300, and an over-voltage comparator 310. The current-command circuit comprises a square circuit 305, a multiplier-divider 320, a resistor 330, an adder 340, and a current-loop error amplifier 350. An input of the square circuit 305 is connected to the line-voltage terminal RMS for receiving the line-effective voltage VRMS. The multiplier-divider 320 comprises a first multiplier input terminal connected to the line-current terminal IAC for receiving the line-reference current IAC, a second multiplier input terminal for receiving the voltage-loop error signal VEA, and a divider input terminal connected to an output terminal of the square circuit 305 for receiving a squared line-effective voltage VRMS2.
The multiplier-divider 320 generates a current command signal ICMD, which is expressed by following equation (1):
                                          I            CMD                    ∝                      k            ×                          (                                                                    I                    AC                                    ×                                      V                    EA                                                                    V                  RMS                  2                                            )                                      ,                            (        1        )            where k is a constant, IAC is the line-reference current, VEA is the voltage-loop error signal, and VRMS is the line-effective voltage.
The adder 340 generates a command signal VX, which is expressed by following equation (2):VX=ICMD×R330+(−VS)  (2)where ICMD is the current command signal, R330 is the resistance of the resistor 330, and −VS is the sense voltage to present the overall system current IS of the PFC converter. The current-loop error amplifier 350 amplifies the command signal VX to generate a current-loop error signal VIEA.
The switching-control circuit of the conventional switching controller 100a comprises an oscillator 110, an inverter 150, a flip-flop 155, an AND gate 160, and a comparator 250. The oscillator 110 generates a pulse signal PLS and a ramp signal RMP. The pulse signal PLS clocks the flip-flop 155 via the inverter 150 to enable the switching signal VG. The comparator 250 compares the current-loop error signal VIEA and the ramp signal RMP. Once the ramp signal RMP is higher than the current-loop error signal VIEA, the switching signal VG is disabled via the flip-flop 155 and the AND gate 160.
In conventional PFC converter, when the input voltage VDC is 90 VDC, for example, the bulk voltage VBULK is boosted up to around 380 VDC irrespective of load conditions of the PFC converter. As the load decreases to a light-load condition, the bulk voltage VBULK of the PFC converter in the related arts remains at 380 VDC, for example, in a first level. This lowers the conversion efficiency because a level of the bulk voltage VBULK to sufficiently supply the load is only 300 VDC, for example, a second level. Redundant power consumption is therefore wasted on the switching loss of the power switch 70 and the power loss of the rectifier 30.
To avoid redundant power consumption and achieve higher efficiency of the PFC converter, the programmable feedback circuit of the conventional switching controller 100a is utilized to regulate the bulk voltage VBULK between the first level and the second level in response to the load conditions of the PFC converter. The programmable feedback circuit comprises a current source 260, a switch 261, and a voltage-loop error amplifier 200. The current source 260 is supplied with a supply voltage VCC. The switch 261 is connected between the current source 260 and a negative input terminal of the voltage-loop error amplifier 200. The negative input terminal of the voltage-loop error amplifier 200 is connected to the feedback terminal FB of the conventional switching controller 100a and the voltage divider 50. A positive input terminal of the voltage-loop error amplifier 200 is supplied with a feedback threshold VR. An output terminal of the voltage-loop error amplifier 200 is connected to the compensation terminal EA.
The conventional switching controller 100a further comprises a light-load detector 300 to receive the voltage-loop error signal VEA and the pulse signal PLS to generate a power-saving signal SE. The light-load detector 300 has a hysteresis characteristic with an upper threshold VTH(H) and a lower threshold VTH(L). Once the voltage-loop error signal VEA is lower than the lower threshold VTH(L), a light-load condition of the load will be detected. The power-saving signal SE is enabled when the light-load detector 300 detects the light-load condition. The switch 261 is controlled by the power-saving signal SE. Under normal/heavy load conditions, the power-saving signal SE is disabled, and the bulk voltage VBULK is regulated at a first level VBULK1 (as shown in FIG. 3) in response to the voltage-loop error signal VEA. As the light-load condition is detected by the light-load detector 300, the power-saving signal SE is enabled to turn on the switch 261. The current source 260 provides a programming current IQ toward the voltage divider 50. The increased feedback voltage VFB at the negative input terminal of the voltage-loop error amplifier 200 regulates the bulk voltage VBULK from the first level VBULK1 toward a second level VBULK2 (as shown in FIG. 3). As the load increases to the normal/heavy load condition, the power-saving signal SE is disabled to turn off the switch 261, and the programming current IQ is terminated in response thereto. The feedback voltage VFB at the negative input terminal of the voltage-loop error amplifier 200 is therefore decreased to regulate the bulk voltage VBULK from the second level VBULK2 toward the first level VBULK1 again (as shown in FIG. 3).
However, voltage undershooting occurs as shown in dotted circles W and X of FIG. 3. A first voltage undershooting (in the dotted circle W) occurs at the transient that the bulk voltage VBULK decreases to arrive at the second level VBULK2 from the first level VBULK1. A second voltage undershooting (in the dotted circle X) occurs at the transient that the bulk voltage VBULK starts to increase toward the first level VBULK1 from the second level VBULK2.
Referring to both FIG. 2 and FIG. 3, the first voltage undershooting (in the dotted circle W) is explained as follows. As the load at the output of the PFC converter decreases, the feedback voltage VFB at the feedback terminal FB of the switching controller 100a increases in response to the increment of the bulk voltage VBULK. Since the feedback voltage VFB is supplied to the negative input terminal of the voltage-loop error amplifier 200, the voltage-loop error signal VEA generated by the voltage-loop error amplifier 200 is inversely proportional to the feedback voltage VFB. When the voltage-loop error signal VEA is lower than the lower threshold VTH(L), the power-saving signal SE is enabled to turn on the switch 261. The programming current IQ flows toward the voltage divider 50 as shown in FIG. 1. This further increases the feedback voltage VFB. The voltage-loop error signal VEA drops to zero from the lower threshold VTH(L) as the feedback voltage VFB exceeds the feedback threshold VR. When the feedback voltage VFB exceeds an over-voltage threshold VOVP, the over-voltage comparator 310 generates an over-voltage signal SOV to disable the switching signal VG via the AND gate 160. The waveform of the input voltage VDC will become direct-current waveform from full-wave rectified waveform. As period T1 illustrates, the line-effective voltage VRMS is charged to reach its maximum level VRMS(MAX) via an RC network of the low-pass filter 80 in FIG. 1 by the input voltage VDC.
The bulk voltage VBULK starts to linearly decrease from the first level VBULK1 because the switching signal VG is disabled. The feedback voltage VFB then linearly decreases in response to the decrement of the bulk voltage VBULK. Once the feedback voltage VFB drops to around the feedback threshold VR, an output current of the voltage-loop error amplifier 200 begins to charge up the compensation capacitor 45 via the compensation terminal EA. As period T2 illustrates, the voltage-loop error signal VEA is charged up with a slope determined by the output current of the voltage-loop error amplifier 200 and the capacitance of the compensation capacitor 45. Referring to equation (1) described above, the magnitude of the current-command signal ICMD is relatively small due to the excessive line-effective voltage VRMS and the slow response of the voltage-loop error signal VEA. A small current-command signal ICMD decreases an input current IDC. This causes insufficient energy transmission to maintain the bulk voltage VBULK at the second level VBULK2. The first voltage undershooting therefore occurs as shown in the dotted circle W.
In addition to the first voltage undershooting, a faulty operation of the bulk voltage VBULK is discussed as follows. Normally, the voltage-loop error signal VEA is charged up and stops at the lower threshold VTH(L). Unfortunately, further referring to equation (1), in order to keep the current-command signal ICMD constant, the current loop of the conventional switching controller 100a continues increasing the voltage-loop error signal VEA until it arrives at the upper threshold VTH(H), as period T3 illustrates.
When the voltage-loop error signal VEA exceeds the upper threshold VTH(H), the power-saving signal SE is disabled to terminate the programming current IQ. This dramatically pulls down the feedback voltage VFB and therefore linearly pulls up the bulk voltage VBULK in error, as the bold dotted waveform shows.
The second voltage undershooting (in dotted circle X) is also explained as follows. As the load of the PFC converter increases, the voltage-loop error signal VEA will gradually increase in response to the load increment, as period T4 illustrates. When the voltage-loop error signal VEA exceeds the upper threshold VTH(H), the power-saving signal SE is disabled to turn off the switch 261. The programming current IQ is then terminated and the feedback voltage VFB therefore drops to a voltage level VR0. The feedback threshold VR and the voltage level VR0 are respectively expressed by following equations (3) and (4):
                              V          R                =                                            I              Q                        ×                          (                                                                    R                    51                                    ×                                      R                    52                                                                                        R                    51                                    +                                      R                    52                                                              )                                +                                    V              BULK                        ×                          (                                                R                  52                                                                      R                    51                                    +                                      R                    52                                                              )                                                          (        3        )                                                      V                          R              ⁢                                                          ⁢              0                                =                                                    V                R                            -                              Δ                ⁢                                                                  ⁢                V                                      =                                          V                R                            -                              [                                                      I                    Q                                    ×                                      (                                                                                            R                          51                                                ×                                                  R                          52                                                                                                                      R                          51                                                +                                                  R                          52                                                                                      )                                                  ]                                                    ,                            (        4        )            where IQ is the programming current, R51 and R52 are respectively the resistance of the resistors 51 and 52, and ΔV is the difference between the feedback threshold VR and the voltage level VR0.
As period T5 illustrates, the voltage-loop error signal VEA continues to be charged up to its maximum magnitude VEA(MAX) which is capable of maximizing the current-command signal ICMD to pull up the bulk voltage VBULK without voltage undershooting. Limited to the slow response of the voltage-loop error signal VEA, as the load of the PFC converter draws power from the PFC converter, the second voltage undershooting occurs as shown in the dotted circle X.
Voltage undershooting at the bulk voltage of the PFC converter incurs insufficient power supply required by the load, such as the PWM circuit 60. This might cause a brownout condition for the PWM circuit 60. Even though the related art as mentioned above solves the problem of redundant power consumption under light-load condition for the PFC converter, it still fails to overcome the voltage undershooting problem.
As a result, there is a need to provide a PFC converter not only capable of regulating the bulk voltage in response to different load conditions but also smoothly regulating the bulk voltage without voltage undershooting.